In miniaturizing semiconductor devices, shallow diffusion regions are formed and a method of manufacturing a transistor is more and more complicated. Moreover, it may also be required to form an analog circuit, a delay circuit, an integral circuit, and a capacitance element such as a memory cell capacitor in order to form a semiconductor integrated circuit.
As the capacitance element described above, a MIS capacitor is widely used under the condition that a semiconductor substrate in which impurities are doped to a higher concentration, is used as a lower electrode.
In this MIS capacitor, an impurity diffusion region which will become a lower electrode is formed by implanting impurity ions in the semiconductor substrate. Next, a capacitor insulation film is formed on the impurity diffusion region by a thermal oxidation method. Thereafter, an upper electrode of the MIS capacitor is formed by patterning polysilicon on a capacitor insulation film. The upper electrode is formed simultaneously with forming a gate polysilicon electrode of a MIS transistor
Here, the impurity concentration for the lower capacitor electrode is higher by about 100 times than the impurity concentration for the ordinary MIS transistor channel and therefore a depletion layer is not easily formed in the semiconductor substrate. Accordingly, the capacitor impurity diffusion region has a merit that dependence of capacitance on voltage is extremely small. Moreover, since the thermal oxidation method is utilized, a comparatively thinner capacitor insulation film can be formed stably. Therefore, it is possible to obtain a capacitor which is suitable for an analog circuit, which requires higher accuracy and has a large capacitance per unit area. Moreover, since the capacitor is formed together with the MIS transistor, such capacitor can be manufactured at a low price.
The above described MIS capacitor is described, for example, in Japanese Published Unexamined Patent application No. 1996-97363 (Published on Apr. 12, 1996) Corresponding U.S. Pat. No. 5,973,381 A (Published on Oct. 26, 1999)
However, with further miniaturization of semiconductor devices, it is now difficult to improve both the characteristics of a gate insulation film and the characteristics of the capacitor insulation film because the MIS transistor and the MIS capacitor are simultaneously formed.
Thickness of the gate insulation film in the generation of 90 nm must be set to 2 nm or less. To form a thinner gate insulation film, which has a higher quality, it has been proposed to conduct hydrogen annealing before forming the gate insulation film. A thin naturally oxidized film formed on the surface of a semiconductor substrate can be removed by conducting hydrogen annealing and thereby an ultra-thin gate insulation film of the excellent film quality can be formed.
However, it has been proved that when the hydrogen annealing is utilized, excellent characteristics cannot be attained simultaneously in both devices only by simultaneously forming the MIS transistor and the MIS capacitor. Accordingly, it is required to provide a method of forming the MIS capacitor which can cover the progress in miniaturization.